module NRZ_to_Manchester_Moore(
    output reg B_out,
    input B_in,
    input clk,reset_b
);
    parameter S_0=2'b00,
        S_1=2'b01,
        S_2=2'b10,
        S_3=2'b11,
        dont_care_state=2'bxx,
        dont_care_out=1'bx;
    reg[1:0] state, next_state;
    always @(posedge clk or negedge reset_b)
        if(!reset_b)
            state<=S_0;
        else
            state<=next_state;
    always @(state)begin
        case(state)
            S_0:if(B_in)
                next_state=S_1;
            else
                next_state=S_2;
            S_1:
                next_state=S_3;
            S_2:
                next_state=S_0;
            S_3:if(B_in)
                next_state=S_1;
            else
                next_state=S_2;
        endcase
    end
    always @(next_state)begin
        B_out=0;
        case(next_state)
            S_0:B_out=1;
            S_1:B_out=1;
            S_2:B_out=0;
            S_3:B_out=0;
        endcase
    end
endmodule