/*The Mealy type state machine output is not only related to the current state, but also related to the input*/
module NRZ_to_Manchester_Mealy(
    output reg B_out,
    input B_in, clk, reset_b
);
    parameter S_0=2'd0,
        S_1=2'd1,
        S_2=2'd2,
        dont_care_state=2'bx,
        dont_care_out=1'bx;
    reg[1:0] state, next_state;
    always@(posedge clk or negedge reset_b)
        if(!reset_b)
            state<=S_0;
        else
            state<=next_state;
    always @(state, B_in)begin
        //The sensitive list here is best not to include B_IN, otherwise there will be invalid output
        //The Mealy type state machine output is related to the input, but does not necessarily change from input, only
        //Different changes due to input
        B_out=0;
        case(state)
            S_0:if(B_in)begin
                B_out=1;
                next_state=S_1;
            end
            else
                next_state=S_2;
            S_1:
                next_state=S_0;
            S_2:begin
                next_state=S_0;
                B_out=1;
            end
            default:begin
                next_state=dont_care_state;
                B_out=dont_care_out;
            end
        endcase
    end
endmodule

module NRZ_to_Manchester_Mealy_tb;
    reg clk, reset_b;
    reg B_in;
    wire B_out;
    
    reg count;
    
    initial begin
        clk=0;
        reset_b=1;
        B_in=0;
        count=0;
        #20 reset_b=0;
        #10 reset_b=1;
        #10000 $finish;
    end
    
    initial begin
        $dumpfile("dump.lxt");
        $dumpvars(0,NRZ_to_Manchester_Mealy_tb);
    end

    initial
        forever #10 clk=!clk;

    always @(posedge clk)
        count=count+1;
    always @(negedge clk)
        if(count)
            B_in={$random}%2;
    
    NRZ_to_Manchester_Mealy uut(
        .B_out(B_out),
        .B_in(B_in),
        .clk(clk),
        .reset_b(reset_b)
    );
endmodule